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| 82503 DUAL SERIAL TRANSCEIVER (DST) 82503 PRODUCT FEATURE SET OVERVIEW Y Single Component Ethernet Interface to Both 802 3 10BASE-T and AUI Automatic or Manual Port Selection Manchester Encoder Decoder and Clock Recovery No Glue Interface to Industry-Standard LAN Controllers Intel 82586 82590 82593 and 82596 AMD 7990 (LANCE ) National Semiconductor 8390 and 83932 (SONIC ) Western Digital 83C690 Fujitsu 86950 (Etherstar ) Y Y Y Y Y Diagnostic Loopback Reset Low Power Modes Network Status Indicators Defeatable Jabber Timer User Test Modes 10 MHz Transmit Clock Generator One Micron CHMOS Technology Single 5-V Supply IV (Px48) Y Y Y Y Y Y INTERFACE FEATURES TPE Y AUI Y Y Y Complies with 10BASE-T IEEE Std 802 3i-1990 for Twisted Pair Ethernet Selectable Polarity Switching Direct Interface to TPE Analog Filters On-Chip TPE Squelch Defeatable Link Integrity (LI) Support of Cable Lengths l 100m Complies with IEEE 802 3 AUI Standard Direct Interface to AUI Transformers On-Chip AUI Squelch Y Y Y Y Y A block diagram of a typical application is shown in Figure 1 The 82503 Dual Serial Transceiver is a high-integration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE 802 3 local area network applications (10BASE5 10BASE2 and 10BASE-T) The component supports both an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE) It allows OEMs to design a state-of-the-art media interface that is jumperless and fully automatic The 82503 includes on-chip AUI and TPE drivers and receivers it offers designers a cost-effective integrated solution for interfacing LAN controllers to the wire medium CHMOS is a patented process of Intel Corporation Ethernet is a registered trademark of Xerox Corporation LANCE is a registered trademark of Advanced Micro Devices Etherstar is a registered trademark of Fujitsu Electronics Sonic is a registered trademark of National Semiconductor Corporation Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 October 1995 Order Number 290421-004 82503 Dual Serial Transceiver (DST) CONTENTS 1 0 82503 PRODUCT FEATURES 2 0 PIN DEFINITION 2 1 Power Pins 2 2 Clock Pins 2 3 AUI Pins 2 4 TPE Pins 2 5 Controller Interface Pins 2 6 Mode Pins 2 7 LED Pins 3 0 82503 ARCHITECTURE 3 1 Clock Generation 3 2 Transmit Blocks 3 3 Receive Blocks 3 4 Collision Detection 3 5 Link Integrity 3 6 Jabber Function 3 7 TPE Loopback 3 8 SQE Test Function 3 9 Port Selection 3 10 LED Description 3 11 Polarity Switching 3 12 Controller Interface PAGE 3 5 6 6 6 7 7 8 9 10 10 10 11 13 13 13 13 14 14 14 14 15 CONTENTS PAGE 16 16 16 16 16 17 17 17 17 19 20 4 0 RESET LOW POWER AND TEST MODES 4 1 Reset 4 2 Low Power and High Impedance Modes 4 3 Diagnostic Loopback 4 4 Customer Test Modes (Continuous AUI TPE Transmit) 5 0 APPLICATION EXAMPLE 5 1 Introduction 5 2 Design Guidelines 5 3 Layout Guidelines 6 0 PACKAGE THERMAL SPECIFICATIONS 7 0 ELECTRICAL SPECIFICATIONS AND TIMINGS 2 82503 290421 - 1 Figure 1 Application Block Diagram 10 82503 PRODUCT FEATURES terization The predistortion circuitry eliminates line overcharge and reduces jitter on 10BASE-T links The 82503 can also support twisted pair cable lengths of up to 200m when placed in TPE Extended Squelch Mode (XSQ) This component incorporates six LED drivers to display transmit data receive data collision link integrity polarity faults and port selections allowing for complete network monitoring by the user The transmit receive and collision LEDs indicate the rate of activity by the frequency of flashing The 82503 also has a low power mode During low power many of the 82503's pins are in a high-impedance state to facilitate board-level testing The 82503's diagnostic loopback control enables it to route a transmission signal from the LAN controller through its Manchester encoder-decoder circuitry and back to the LAN controller This provides effective network node fault detection and isolation capabilities In addition the 82503 supports diagnostic test modes that generate continuous tranmission of data through the twisted pair port allowing designers to measure the analog performance of their design The 82503 is available in 44-lead PLCC and 44-lead QFP packages and is fabricated with Intel's lowpower high-speed CHMOS IV technology using a single 5-V supply The 82503 incorporates all the active circuitry required to interface Ethernet controllers to 10BASE-T networks or the attachment unit interface (AUI) It supports a direct no-glue interface to Intel's family of high-performance LAN controllers (82586 82590 82593 and 82596) The 82503 also provides a direct no-glue interface to the National Semiconductor 8390 and 83932 (SONIC) the Western Digital 83C690 the Advanced Micro Devices 7990 (LANCE) and 79C900 (ILACC) and the Fujitsu 86950 (Etherstar) controllers This component includes three advanced features jumperless two-port design capability automatic port selection and polarity switching The jumperless TPE or AUI port selection capability allows designers maximum ease-of-use and network flexibility Automatic port selection ensures complete software compatibility with existing 10BASE2 and 10BASE5 software drivers The 82503's polarity switching feature will detect and correct polarity errors on the twisted pair the most common wiring fault in twisted pair networks The 82503 contains all the circuitry needed to meet the 10BASE-T specification including link integrity a jabber timer and internal predistortion Deselecting link integrity allows the component to be used in some prestandard networks The 82503's jabber timer prevents the station from continuously transmitting and is defeatable for simple design charac- 3 82503 290421 - 2 Figure 2 82503 Functional Block Diagram 4 82503 20 PIN DEFINITION 290421 - 3 Figure 3 44-Lead PLCC Pin Configuration 290421 - 44 Figure 4 44-Lead QFP Pin Configuration 5 82503 2 1 Power Pins Symbol VSS(1) VCC (1) PLCC Pin 7 17 39 6 18 40 28 29 QFP Pin 1 11 33 44 12 34 22 23 Type Supply Supply Supply Supply Name and Function Digital Ground Digital VCC A 5-V g 5% Power Supply Analog VCC A 5-V g 5% Power Supply Analog Ground VCCA(1) VSSA(1) NOTE 1 VCC and VCCA must be connected to the same power supply VSS and VSSA must be connected to the same ground Separate decoupling and noise conditioning (e g ferrite beads) should be used 2 2 Clock Pins Symbol X1 X2 PLCC Pin 21 20 QFP Pin 15 14 Type I O Name and Function CLOCK CRYSTAL A 20 MHz crystal input This pin can be driven with an external MOS level clock when X2 is left floating CLOCK CRYSTAL A 20 MHz crystal output X1 can be driven with an external MOS level clock when this pin is left floating 2 3 AUI Pins Symbol TRMT TRMT PLCC Pin 27 26 QFP Pin 21 20 Type O O Name and Function TRANSMIT PAIR A differential output driver pair that drives the transmit pair of the transceiver cable The output bit stream is Manchester encoded Following the last transition which is positive at TRMT the differential voltage is reduced to zero volts RECEIVE PAIR A differentially driven input pair which is tied to the receive pair of the Ethernet transceiver cable The first transition on RCV is negative-going to indicate the beginning of the frame The last transition is positive-going to indicate the end of the frame The received bit stream is assumed to be Manchester encoded COLLISION PAIR A differentially driven input pair tied to the collision presence pair of the Ethernet transceiver cable The collision presence signal is a 10 MHz square wave The first transition at CLSN is negative-going to indicate the beginning of the signal the last transition is positive-going to indicate the end of the signal RCV RCV 31 30 25 24 I I CLSN CLSN 25 24 19 18 I I 6 82503 2 4 TPE Pins Symbol TDH TDH TDL TDL PLCC Pin 35 37 34 36 QFP Pin 29 31 28 30 Type O O O O Name and Function TP TRANSMIT PAIR DRIVERS These four outputs constitute the twisted-pair drivers which have predistortion capabilities The TDH TDH outputs generate the 10 Mb s Manchester Encoded data The TDL TDL outputs mirror the TDH TDH outputs except for fat bit occurrences (100 ns pulses) During the second half of a fat bit (either high or low) the TDL TDL outputs are inverted with respect to TDH TDH outputs This signal behavior reduces the amount of jitter by preventing overcharge on the twisted pair medium TP RECEIVE PAIR The differential twisted pair receiver The receiver pair is connected to the twisted pair medium and is driven with 10 Mb s Manchester encoded data RD RD 32 33 26 27 I I 2 5 Controller Interface Pins Symbol TxC PLCC Pin 9 QFP Pin 3 Type O Name and Function TRANSMIT CLOCK A 10 MHz clock output tied directly to the transmit clock pin of the Ethernet controller Changes sense depending on controller selected Active low for Intel and Fujitsu controller interfaces active high for National and AMD interfaces Can drive one TTL load TRANSMIT DATA TTL input NRZ serial data is clocked in on TxD from the Ethernet controller Connects directly to the transmit data pin of the Ethernet controller REQUEST TO SEND TTL input An active low input signal synchronous to TxC which enables data transmission on the active port Changes sense depending on controller selected Active low for the Intel controller interface active high for National AMD and Fujitsu interfaces RECEIVE CLOCK A 10 MHz clock output tied directly to the receive clock pin of the Ethernet controller This clock is the recovered clock from incoming data on the active port Changes sense depending on controller selected Active low for Intel and Fujitsu controller interfaces active high for National and AMD interfaces Can drive one TTL load RECEIVE DATA Received NRZ data (synchronous to RxC) passed to the Ethernet controller Connect directly to the receive data pin of the controller Can drive one TTL load CARRIER SENSE Output that alerts the Ethernet controller that data is present on the active port Connects directly to the carrier sense pin of the Ethernet controller Changes sense depending on controller mode selected Active low for Intel controller interface active high for National AMD and Fujitsu interfaces Can drive one TTL load COLLISION DETECT Output that indicates presence of a collision Connects directly to the collision detect pin of the Ethernet controller Changes sense depending on controller selected Active low for Intel and Fujitsu controller interfaces active high for National and AMD interfaces Can drive one TTL load TxD 16 10 I RTS 15 9 I RxC 14 8 O RxD 13 7 O CRS 10 4 O CDT 12 6 O 7 82503 2 6 Mode Pins Symbol TPE AUI PLCC Pin 2 QFP Pin 40 Type IO Name and Function PORT SELECT TTL input LED output If APORT is low TPE AUI is an input and selects either the TPE port (TPE AUI high) or AUI port (TPE AUI low) If APORT is high the 82503 will indicate the port selected by driving TPE AUI high (TPE) or low (AUI) TPE AUI can drive an LED pull-up AUTOMATIC PORT SELECTION TTL input When high 82503 will automatically select TPE or AUI port based on presence of valid link beats or frames on the TPE receive input Mode selected will be indicated on TPE AUI AUTOMATIC POLARITY CORRECTION EXTENDED SQUELCH ENABLE TTL input When high the extended squelch mode is disabled and automatic polarity correction is enabled Both junctions (APOL and XSQ) are enabled when this pin is at a high impedance state When low both functions become disabled The presence of a polarity fault on the TPE receive pair is indicated on POLED regardless of the state of APOL LINK INTEGRITY DISABLE TTL input If high link integrity function is disabled If low link integrity function is enabled CONTROLLER SELECT Selects the appropriate interface for the desired Ethernet controller When CS0 1 e 0 0 supports Intel controllers When CS0 1 e 0 1 supports Fujitsu controllers When CS0 1 e 1 0 supports Western Digital and National controllers When CS0 1 e 1 1 supports AMD controllers (See Table 2 ) LOOPBACK TTL input An active low input signal that causes the 82503 to enter diagnostic loopback mode The twisted pair or AUI medium will be removed from the circuit thus isolating the node from the network When not connected this pin assumes the inactive (high) state Diagnostic loopback does not disable the operation of the link integrity processor link beat generator or automatic port selection JABBER DISABLE TTL input When high this pin disables the jabber function When low the jabber function is enabled and the device performs AUI or TP jabber protection for the active port If this pin and TEST are asserted during a falling edge of RESET the 82503 enters its low power mode when either this pin or TEST deasserts then the 82503 transitions to its normal operating mode TEST MODE ENABLE TTL input When TEST is high and RESET is deasserted a customer test mode is directly accessed When driven low test mode is disabled If this pin and JABD are asserted during a falling edge of RESET the 82503 enters its low power mode when either this pin or JABD deasserts then the 82503 transitions to its normal operating mode RESET TTL input When high resets internal circuitry On the falling edge of RESET either test mode or low power mode can be entered depending on the state of JABD and TEST APORT 3 41 I APOL XSQ 4 42 I LID CS0 CS1 38 5 8 32 43 2 I I I LPBK 11 5 I JABD 23 17 I TEST 19 13 I RESET 22 16 I 8 82503 2 7 LED Pins Symbol TxLED PLCC Pin 42 QFP Pin 36 Type IO Name and Function TRANSMIT LED LED output Indicates transmit status of the AUI or TPE port Normally off (high) output Turns on to indicate transmission Flashes at a rate dependent on the level of transmit activity Upon entering a customer test mode this pin must be driven high either through an LED or a resistor RECEIVE LED LED output Indicates receive status of the AUI or TPE port Normally off (high) output Turns on to indicate reception Flashes at a rate dependent on the level of receive activity Upon entering a customer test mode this pin must be driven high either through an LED or a resistor COLLISION LED LED output Indicates collision status of the AUI or TPE port Normally off (high) output Turns on to indicate collision Flashes at a rate dependent on the level of collision activity This pin is also used to determine which customer test modes are entered LINK INTEGRITY LED LED output Normally on (low) output which indicates good link integrity on the TPE port during TPE mode Remains on when link integrity function has been disabled Turns off during AUI mode or when link integrity fails in TPE mode Minimum off time is 100 ms minimum on time is set by the link integrity function POLARITY INDICATION LED output If the 82503 detects that the receive TPE wires are reversed POLED will turn on (low) to indicate the fault POLED remains on even if APOL XSQ is high and the 82503 has automatically corrected for the reversed wires RxLED 43 37 IO COLED 44 38 IO LILED 41 35 O POLED 1 39 O NOTE 1 The LED outputs have a weak pull-up capable of sourcing 500 mA They can sink 10 mA while still meeting TTL levels All LEDs can be used as indication pins if no LED is needed Some of these outputs include pulse width conditioning which should be accounted for in software 9 82503 30 82503 ARCHITECTURE 3 2 Transmit Blocks 3 2 1 MANCHESTER ENCODER The 20 MHz clock is used to Manchester-encode data on the TxD input This clock is also divided by two to produce the 10 MHz clock the LAN controller needs for synchronizing its RTS and TxD signals Data encoding and transmission begins with RTS asserting Since the first bit of a transmission is a 1 the first transition is always negative on the transmit outputs (TRMT or TD pins) Transmission ends when RTS deasserts The last transition is always positive at the transmit outputs (TRMT or TD pins) and may occur at the center of the bit cell if the last data bit to be transmitted is a 1 or at the boundary of the bit cell if the last data bit to be sent is a 0 Immediately after the end of a transmission all signals on the RCV pair (when AUI mode is selected) are inhibited for 4 to 5 ms This dead time is necessary for proper operation of the SQE (heartbeat) test 3 2 2 AUI CABLE DRIVER The AUI cable driver (TRMT pair) is a differential circuit which interfaces to the AUI cable through a pulse transformer High voltage protection is achieved by using a transformer to isolate the transmit pins (TRMT pair) from the transceiver cable The total transmit circuit inductance including the 802 3 transceiver transformers should be a minimum of 27 mH for Ethernet applications 3 2 3 TWISTED PAIR CABLE DRIVER The twisted pair line drivers (TD pairs) begin transmitting the serial Manchester bit stream 3 bit times after RTS is asserted The line drivers use a predistortion algorithm to improve jitter performance for up to 100 meters of twisted pair cable The line drivers reduce their drive level during the second half of ``fat'' (100 ns) Manchester pulses and maintain a full drive level during all ``thin'' (50 ns) pulses and during the first half of the ``fat'' pulses This reduces line overcharging during ``fat'' pulses a major source of jitter 3 1 Clock Generation A 20 MHz parallel resonant crystal is used to control the clock generation oscillator which provides the basic 20 MHz clock source An internal divide-bytwo counter generates the 10 MHz g0 01% clock required by the IEEE 802 3 specification We recommend a crystal that meets the following specifications be used Quartz Crystal 20 MHz g 0 002% at 25 C Accuracy g 0 005% over full operating temperature 0 C to a 70 C Parallel resonant with 20 pF Load Fundamental Mode Maximum Series Resistance RSERIES e 30X Several vendors have such crystals either-off-the shelf or custom made Two possible vendors are 1 M-Tron Industries Inc Yankton SD 57078 Specifications Part No HC49 with 20 MHz 50 PPM over 0 C to a 70 C and 20 pF fundamental load 2 Crystek Corporation 100 Crystal Drive Ft Myers FL 33907 Part No 013212 The accuracy of the Crystal Oscillator frequency depends on the PC board characteristics therefore it is advisable to keep the X1 and X2 traces as short as possible The optimum value of C1 and C2 should be determined experimentally under nominal operating conditions The typical value of C1 and C2 is between 22 pF and 35 pF An external 20 MHz MOS-level clock may be applied to pin X1 if pin X2 is left floating 10 82503 290421 - 4 Figure 5 TPE Predistortion 3 3 Receive Blocks 3 3 1 MANCHESTER DECODER AND CLOCK RECOVERY The 82503 performs Manchester decoding and timing recovery of the incoming data in AUI and TPE modes The Manchester-encoded data stream is decoded to separate the Receive Clock (RxC) and the Receive Data (RxD) from the differential signal The 82503 uses an advanced digital technique to perform the decoding function The use of digital circuitry instead of analog circuitry (e g a phase-lock loop) to perform the decoding ensures that the decoding function is less sensitive to variations in operating conditions A high-resolution phase reference is used to digitize the phase of the incoming data bit-center transition The digitizer has a phase resolution of 1 32 of a bit time The digitized phase is filtered by a digital low-pass filter to remove rapid phase variations i e phase jitter Slow phase variations such as those caused by small differences between the data frequency and the clock frequency are not filtered by the lowpass filter The RxC generator digitally sets the phases of the two RxC transitions to respectively lead and lag the bit-center transition by bit time RxC is used to recover RxD by sampling the incoming data with an edge-triggered flip-flop Lock is achieved by reducing the time constant of the digital filter to zero at the start of a new frame Any uncertainty in the bit-center phase of the first transition that is caused by jitter is subsequently removed by gradually increasing the filter time constant during the following preamble By that time the phase of the bit center is output by the filter and lock is achieved Lock is achieved within the first 14 bit times as seen by the AUI inputs The maximum bit-cell timing distortion (jitter) tolerated by the Manchester decoder circuitry is g12 ns (preamble) g18 ns (data) for AUI and g13 5 ns for TPE (data and preamble) 11 82503 290421 - 5 Figure 6 Manchester Decoder and Clock Recovery 3 3 2 AUI RECEIVE AND COLLISION BUFFERS The AUI receive and collision inputs are driven through isolation transformers to provide high voltage protection and DC common mode voltage rejection The incoming signals are converted to digital levels and passed to the Manchester decoder and collision detection circuitry 3 3 3 AUI RECEIVE AND COLLISION SQUELCH CIRCUITS Both the receive (RCV) and collision (CLSN) pairs have the following squelch characteristics devices and EMI filters necessary to conform to the 10BASE-T standards and local RF regulations The input differential voltage range for the TPE receiver is greater than 500 mV and less than 3 1V differential 3 3 5 TPE RECEIVE SQUELCH CIRCUITS The TPE receive buffer distinguishes valid receive differential data link test pulses and the idle condition according to the requirements of the 10BASE-T standard Signals at the output of the EMI filter (thus at the RD and RD pair) are rejected as follows All differential pulses of peak magnitude less than 300 mV are rejected The squelch circuits are turned on at idle A pulse is rejected if the peak differential voltage is more positive than b 160 mV regardless of pulse width A pulse is considered valid if its peak differential voltage is more negative than b 300 mV and its width measured at b 285 mV is greater than 25 ns All continuous sinusoids with a differential amplitude less than 6 2 VPP and a frequency less than 2 MHz are rejected All sine waves of single cycle duration starting with phase 0 or 180 that have an amplitude less than 6 2 VPP and a frequency of 2 MHz to 16 MHz are rejected if the single cycle is preceeded and followed by 4 bit times of silence (i e a signal less than 300 mV) 3 3 6 TPE Extended Squelch Mode By placing the 82503 into TPE extended squelch mode the 82503 can support cable lengths greater than the 100m specified in the 10Base-T IEEE standard (802 3i-1990) The squelch thresholds for the signals at the RD RD pair are typically reduced by 4 5 dB This allows Grade 5 twisted-pair cable to be used to overcome attenuation and multipair crosstalk for cable lengths up to 200 meters The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive (RCV) or the AUI collision (CLSN) pair If a positive differential pulse occurs on either the AUI receive or collision pairs for greater than 160 ns End of Frame (EOF) is assumed and the squelch circuitry is turned on 3 3 4 TPE RECEIVE BUFFER The TPE receive pins (RD and RD) are connected to the twisted pair medium through an analog front end The analog front end contains the line coupling 12 82503 TPE extended squelch mode is enabled by presenting a high-impedance ( l 100 KX) at the APOL XSQ pin This can be done by floating the APOL XSQ pin tying APOL XSQ low through a 100 KX resistor or driving APOL XSQ with a three-state buffer When driven high or low using a TTL driver or a low impedance pull-up or pull-down ( k 2 KX) extended squelch is disabled and the driven level at the APOL XSQ pin determines the state of the polaritycorrection function (APOL XSQ e 1 enables polarity correction APOL XSQ e 0 disables polarity correction) The TPE extended squelch feature is transparent to previous steppings of the 82503 Polarity correction is always enabled when the TPE extended-squelch feature is enabled (APOL XSQ e Z) The APOL XSQ pin senses a high-impedance state by an active-polling circuit implemented at the pin Two small polling devices attempt to pull the APOL XSQ pin up to VCC and down to VSS If the pin is in a high-impedance state the devices will be successful in pulling the APOL XSQ pin high and low If the pin is driven high or low the polling devices will not be able to successfully pull the pin in the opposite direction In this way an internal state machine can correctly determine one of three states of the APOL XSQ pin The pin is polled every 25 6 ms to the twisted pair medium as an indication to the remote MAU that the link is good These pulses will be transmitted 8 ms to 24 ms after the end of the last transmission or link test pulse The link integrity function continuously monitors activity on the receive circuit If neither valid data nor link test pulses are received the link integrity processor declares the link bad and disables transmission and reception on the media loopback and the SQE test function Transmission of link test pulses and monitoring receive activity are not affected The idle time required for the link integrity processor to determine the link is bad is 50 ms to 150 ms Once a frame or a sequence of 2 to 10 valid consecutive link test pulses are detected the Link Integrity Processor declares the link is good and reconnects the transmitter and receiver The link integrity function can be disabled by driving the LID pin high or by disabling automatic port selection (APORT e 0) and selecting the AUI port This option is intended primarily for use with pre10BASE-T networks 3 6 Jabber Function 3 4 Collision Detection 3 4 1 AUI COLLISION DETECTION Collision detection in the AUI mode is performed by the attached transceiver and signalled to the 82503 on the CLSN pair A 10 MHz a 25% or b 15% square wave with transition times between 35 ns and 70 ns indicates the collision The 82503 reports this to the LAN controller on the CDT pin 3 4 2 TPE COLLISION DETECTION Collision detection in the TPE mode is indicated by simultaneous transmission and reception on the twisted pair link segment The CDT signal is asserted for the duration of both RTS and the presence of received data CRS is asserted for the duration of either RTS or the presence of received data During a collision the source of RxD will be the received data If the received data stream ends before the transmit data stream the RxD source will be changed to transmit data stream until it ends The 82503 contains a jabber timer to implement the jabber function If a transmission continues beyond the limits specified the jabber function inhibits further transmission and asserts the collision indicator CDT The limits for jabber transmission are 20 ms to 150 ms in TPE Mode and 8 ms to 16 ms in AUI mode For both AUI and TPE mode the transmission inhibit period extends until the 82503 detects sufficient idle time (between 250 ms and 750 ns) on the RTS signal The jabber function can be disabled by driving the JABD high In TPE mode the link integrity function continues to operate even if the jabber function is inhibiting transmission Link test pulses continue to be sent and the receive circuit continues to be monitored Additionally the link integrity function reconnects to a restored link without waiting for the transmit input to go idle when the jabber function is inhibiting transmission 3 7 TPE Loopback In TPE mode the 82503 implements the transmit to receive loopback (DO to DI) mode specified in the 10BASE-T standard This mode loops back transmitted data through the receive path This function is required to maintain full compatibility with coax MAUs where the data loopback is a natural result of the architecture 3 5 Link Integrity The 82503 supports the link integrity function as defined by 10BASE-T During long periods of idle on the transmitter link test pulses will be transmitted on 13 82503 The transmit to receive loopback function is disabled when the jabber function or link integrity function is inhibiting transmission 3 10 LED Description The 82503 supports six LED pins to indicate the status of important states TPE AUI TxLED POLED LILED RxLED COLED Each pin is capable of directly driving an LED 3 10 1 TPE AUI When automatic port selection is enabled (APORT is high) TPE AUI becomes an LED output and turns off if TPE mode is selected and on if AUI mode is selected 3 10 2 TxLED 3 8 SQE Test Function The 82503 supports the SQE test function when in TPE mode or in Diagnostic Loopback mode The 82503 will assert its CDT pin within 0 6 ms to 1 6 ms after the end of a transmission and it will remain asserted for 5- to 15-bit times If the 82503 is in the TPE mode and is not in diagnostic loopback mode the link integrity function will disable the SQE test function when it detects a bad link 3 9 Port Selection The 82503 features both manual and automatic port selection To enable automatic port selection connect APORT to VCC The 82503 then starts in TPE mode and monitors link integrity If the link is good the 82503 stays in TPE mode and pulls TPE AUI high to indicate that the TPE port was selected If link integrity fails the 82503 switches to AUI mode and pulls TPE AUI low to indicate that the AUI port is now active TPE AUI can drive an LED to indicate port selection (on for AUI off for TPE mode) Note that LILED will be on if TPE mode is selected and off if AUI mode is selected If link integrity is disabled while automatic port selection is enabled the 82503 defaults to TPE mode If the 82503 changes ports while RTS is active transmission is terminated with an End of Frame marker on the old port Transmission of the remaining packet fragment is not allowed on the new port Transmissions will begin with a complete data packet The port can be manually selected by driving APORT low TPE AUI e 0 selects AUI mode and TPE AUI e 1 TPE mode When the port is manually selected the circuitry for the unused port is powered down Changing ports requires 100 ms to allow the circuitry for the new port to resume normal operation Table 1 Port Selection Configuration LID APORT TPE AUI X X 0 1 0 0 1 1 0 1 X X AUI (TPE Port Powered Down) TPE (AUI Port Powered Down) Automatic Port Selection TPE State Transmit status This LED is normally off and flashes at 2 5 Hz 5 Hz and 10 Hz to indicate respectively a low medium and high rate of transmit activity 3 10 3 RxLED Receive LED This LED is normally off and flashes at 2 5 Hz 5 Hz and 10 Hz to indicate respectively a low medium and high rate of receive activity 3 10 4 COLED Collision LED This LED is normally off and flashes at 2 5 Hz 5 Hz and 10 Hz to indicate respectively a low medium and high rate of collision activity 3 10 5 POLED Polarity Fault This LED is normally off and turns on to indicate a polarity fault in the receive pair of the 10BASE-T link Operation of this pin is not affected by the state of the polarity correction function (APOL XSQ e X) 3 10 6 LILED Link Integrity status When Aport is enabled (APORT e 1) this LED is normally on (driven low) to indicate the presence of a valid 10BASE-T link when the TPE port is active The LED will turn off (driven high) when the link fails When link integrity is disabled (LID e 1) while APORT is enabled (APORT e 1) this LED is turned on (driven low) If APORT is disabled (APORT e 0) and the AUI port is manually selected (TPE AUI e 0) the LED output is tristated NOTE TPE AUI is an output pin when APORT e 1 3 11 Polarity Switching In TPE mode the 82503 monitors receive link beats and end-of-frame delimiters for a possible receiver 14 82503 290421 - 6 Figure 7 Polarity Fault State Diagram polarity error due to crossed wires If Pin 4 of the 82503 is high and the TPE receive pins are reversed the 82503 will correct the error by reversing the signals internally and turn POLED on (low) to indicate that the fault has been detected and corrected The polarity correction function is defeatable by driving the APOL XSQ input low However the polarity fault will continue to be indicated on the POLED The 82503 also works with other Ethernet controllers without additional components including the National Semiconductor 8390 and 83932 (SONIC) Western Digital 83C690 Fujitsu 86950 (Etherstar) depending on the state of and CS0 and CS1 inputs The interface of the 82503 to the AMD 7990 (LANCE) requires external logic to control the LPBK pin of the 82503 Note that when an AMD LAN controller is used to interface to the 82503 the LPBK pin of the 82503 becomes active high That is the 82503 enters diagnostic loopback mode when LPBK pin is high and is in normal operation mode when LPBK pin is low The logic sense of the 82503 controller pins will change and should be connected to the controller pins according to the following table 3 12 Controller Interface Connecting the 82503 to one of the Intel Ethernet controllers (82586 82590 82593 82596) requires no additional components Simply drive CS0 and CS1 both low and connect TxC TxD RTS RxC RxD CRS CDT and LPBK to the corresponding controller pins 15 82503 Table 2 Controller Interface Selection 82503 Pin CS0(1) CS1 Pin TxC TxD RTS RxC RxD CRS CDT LPBK Pin TxC TxD RTS RxC RxD CRS CDT LPBK Intel Controller 825XX 0 0 Sense Low High Low Low High Low Low Low Pin TXC TXD TXE RXC RXD CRS COL LPBK National WD Controllers 8390 83C690 83832 (SONIC) 1 0 Sense High High High High High High High High Pin TCLK TX TENA RCLK RX RENA CLSN AMD Controller 7990 (LANCE) 79C900 (ILACC) 1 1 Sense High High High High High High High Pin TCKN TXD TEN RCKN RXD XCD XCOL LPBK Fujitsu Controllers 86950 (Etherstar) 0 1 Sense Low High High Low High High Low High (Note 2) NOTES 1 CS0 and CS1 are intended to be static pins only Switching CS0 and CS1 during network reception or transmission will produce unpredictable results 2 Refer to Section 3 12 40 RESET LOW-POWER AND TEST MODES 4 3 Diagnostic Loopback This is a diagnostic test mode to help in fault isolation and detection Serial NRZ data input on TxD is Manchester encoded and then looped back through the Manchester decoder (TMD) appearing at the RxD output Collision detect is asserted following each transmission to simulate the SQE test Output cable drivers and input amplifiers are disconnected from the controller interface pins while in this mode The link integrity and polarity fault detection functions are not inhibited by diagnostic loopback mode If otherwise enabled they continue to function 4 1 Reset When RESET is asserted the device resets its internal circuits RESET is required after power up and before data can be transmitted or received It is allowed any time thereafter but any existing receive or transmit activity will be lost and all state machines (Link integrity Jabber and Polarity Correction) return to their initial states TEST must be held low for a device reset to prevent entering a test for low power mode During RESET TxC continues without interruption (in Fujitsu mode both TxC and RxC run continuously) 4 4 Customer Test Mode (Continuous AUI TPE Transmit) In this mode the 82503 continuously transmits data without the intervention of a LAN controller Transmission is at 10 MHz (11-bit pattern) and can occur on either the TPE or AUI port The jabber timer is disabled in this mode allowing users to easily test the 10BASE-T harmonic content specification and the quality of their analog front end design without complex software exercisers Customer Test Mode and Low Power Mode are selected at the deassertion of RESET as shown in the following table (Note that the 82503 must be in nonloopback mode before it can enter the customer test mode ) 4 2 Low Power and High Impedance Modes When RESET is deasserted while both TEST and JABD are held high the 82503 enters its low power and high impedance modes The majority of internal circuitry is powered down and many inputs and outputs are three-stated These pins are APORT APOL XSQ LID TPE AUI POLED LILED RTS LPBK RxD TxD CRS and CDT When either JABD or TEST is deasserted the device begins a power on cycle which lasts less than 1 ms During this cycle all inputs are ignored and all transmissions are disabled If RTS is active when the device returns to normal operation the remainder of that packet fragment is not transmitted Normal transmissions are resumed at the start of the first complete data packet 16 82503 Table 3 Test and Low Power Mode Selection RESET TEST 0 1 1 JABD X 0 1 TxLED(1) X 1 X RxLED(1) X 1 X COLED(1) X 1 X Mode Selected Normal Mode Cont Tx 10 MHz Low Power v v v NOTE 1 A standard LED connection to these pins is sufficient to pull them to a logic 1 The port on which the continuous transmit appears is determined by the APORT and TPE AUI pins If automatic port selection is enabled (APORT e 1) then the TPE port broadcasts the continuous transmit If manual port selection is enabled (APORT e 0) then TPE AUI selects the port (1 for TPE 0 for AUI) Test mode is disabled when TEST is deasserted and the device is reset Terminating Resistors The terminating resistors used across the receive and collision pairs are recommended to be 78 7 X g1% Analog Front-End The 82503 provides six TPE pins (TDH TDH TDL TDL RD and RD) that connect to the Analog Front End through a resistor summing network (Figure 7) AFE solutions can be made discretely or purchased from several manufacturers Two different solutions are described in Application Note 356 The example shown here uses a Pulse Engineering AFE package PE65434 which includes EMI filter isolation transformer and common mode choke The output of the AFE connects directly to the 10BASE-T connector (RJ-45) Decoupling It is recommended that 0 01 mF X7R and 0 001 mF NPO decoupling capacitors be placed between the VCCA and VCCD of the 82503 to VSSA and VSSD Clock Generation 50 APPLICATION EXAMPLE 5 1 Introduction The 82503 is designed to work directly with the Intel LAN controllers (82586 82590 82593 and 82596) as well as AMD's Am7990 National Semiconductor's 8390 Western Digital's 82C690 and Fujitsu's 86950 The serial interface signals connect directly between one of the aforementioned LAN controllers and the 82503 without the need for external logic This example is targeted toward interfacing the 82503 to the Intel 82596 in a two-port (TPE AUI) application 5 2 Design Guidelines AUI Pulse Transformer In order to meet the 16V fault tolerance specification of 802 3 a pulse transformer is recommended for the transmit receive and collision pairs The transformer should be placed between the TRMT RCV and CLSN pairs of the 503 and the DO DI and CI pairs respectively of the AUI (DB-15 connector) The pulse transformer should have a parallel inductance of 75 mH minimum (100 mH recommended) Several vendors stock such transformers Two possible vendors are 1 Pulse Engineering (P N PE-64103) 2 Valor Electronics (P N LT6003) The clock input to the 82503 can be from a clock oscillator or a crystal If a clock oscillator is used X1 should be driven and X2 left floating If a crystal oscillator is used refer to Section 3 1 for crystal specifications A complete 82596 82503 TPE AUI Ethernet Solution is shown at the end of this section 5 3 Layout Guidelines General The analog section as well as the entire board itself should conform to good high-frequency practices and standards to minimize switching transients and parasitic interaction between various circuits To achieve this the following guidelines are presented 17 82503 290421 - 7 Figure 8 Application Example Schematic 18 82503 Make power supply and ground traces as thick as possible This will reduce high-frequency cross coupling caused by the inductance of thin traces Connect logic and chassis ground together Separate and decouple all of the analog and digital power supply lines Close signal paths to ground as close as possible to their sources to avoid ground loops and noise cross coupling Use high-loss magnetic beads on power supply distribution lines Crystal The crystal should be adjacent to the 82503 and trace lengths should be as short as possible The X1 and X2 traces should be symmetrical 82503 Analog Differential Signals The differential signals from the 82503 to the transformers analog front end and the connectors should be symmetrical for each pair and as short as possible Differential signal layout should be performed to a characteristic impedance of 78X (for AUI) or 100X (for TPE) As a general rule the trace widths should be one to three times the distance between the PCB layers to eliminate excessive trace inductance The differential signals should also be isolated from the high speed logic signals on the same layer as well as on any sublayers of the PCB Group each of the circuits together but keep them separate from each other Separate their grounds In layout the circuitry from the connectors to the filter network should have the ground plane removed from beneath it This will prevent ground noise from being induced into the analog front end All trace bends should not exceed 45 degrees 60 PACKAGE THERMAL SPECIFICATIONS The 82503 Dual Serial Transceiver is specified for operation when case temperature (TC) is within the range of 0 C to a 85 C The case temperature can be measured in any environment to determine if the 82503 is within the specified operating range The case temperature should be measured at the center of the top surface opposite the pins The acceptable operating ambient temperature (TA) is guaranteed as long as TC is not violated The ambient temperature can be calculated from the ija and ijc from the following equations TJ e TC a P c ijc TJ e TA a P c ija TA e TC b P c (ija b ijc) Values for ija and ijc are given in Table 4 for the 44lead PLCC and 44-lead QFP packages Various values for ija at different airflows Table 5 shows the maximum TA allowable (without exceeding TC) at various airflows Table 4 Thermal Resistance ( C Watt) ijc and ija ija vs Airflow ft min (m s) Package ijc 0 200 400 600 800 1000 (0) (1 01) (2 03) (3 04) (4 06) (5 07) 44-Lead 19 57 PLCC 44-Lead 26 98 QFP 48 94 43 78 41 70 39 66 37 64 Table 5 Maximum TA at Various Airflows ija vs Airflow Package 44-Lead PLCC 44-Lead QFP ft min (m s) 0 200 400 600 800 1000 (0) (1 01) (2 03) (3 04) (4 06) (5 07) 66 49 71 51 73 59 74 63 75 65 76 66 19 82503 70 ELECTRICAL SPECIFICATIONS AND TIMINGS NOTICE This is a production data sheet The specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Case Temperature Under Bias Storage Temperature All Output and Supply Voltages All Input Voltages 0 C to a 85 C b 65 C to a 140 C b 0 5V to a 7V b 1 0V to a 6 0V(1) WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability DC CHARACTERISTICS Symbol VIL(TTL)(2) VIH(TTL)(2) ILI(2) VOL(MOS)(3) VOH(MOS) VOL(LED)(4) VOH(LED) ILP RDIFF VIDF(TPE)(7) (TC e 0 C to a 85 C VCC e 5V g5% VCCA e 5V g5%) Min b0 3 Parameter Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Leakage Current Low Power Mode(5) Input Differential Resistance(6) Input Differential Accept Input Differential Reject Input Differential Accept (XSQ) Input Differential Reject (XSQ) Output Source Resistance Input Differential Accept Input Differential Reject Output Differential Voltage Max 08 VCC g10 Units V V mA V V Test Conditions 20 0 0V s VI s VCC RESET e 1 IOL e 4 mA IOH e b 500 mA IOL e 10 mA IOH e b 500 mA 0 0V s VI s VCC dc 5 MHz s f s 10 MHz 0 45 39 0 45 39 g10 V V mA kX 10 g0 500 g3 1 g0 300 g3 1 g0 180 (Note 8) 6 g0 300 VP VP VP VP X VP VP V RS(TPE)(8) VIDF(AUI)(9) VODF(AUI)(10) 13 g1 5 g0 160 lILOADl e 25 mA g0 450 g1 20 NOTES 1 The voltage levels for RCV CLSN and RD pairs are b0 75V to a 8 5V 2 TTL Input Pins TxD RTS TPE AUI APORT APOL XSQ LID CS0 CS1 LPBK JABD TEST RESET 3 MOS Output Pins TxC RxD RxC CRS CDT 4 LED Pins TPE AUI TxLED RxLED COLED POLED LILED VOL measured 10 ns after falling edge of TxC 5 Pins APORT APOL XSQ LID TPE AUI POLED LILED RTS LPBK RxD TxD CRS CDT CS0 CS1 JABD TEST and RESET 6 Pins RD to RD RCV to RCV and CLSN to CLSN 7 TPE Input Pins RD and RD See Section 3 3 4 and Section 3 3 5 8 Typically it is b4 5 dB below normal squelch level 9 TPE Output Pins TDH TDH TDL and TDL RS measures VCC or VSS to Pin 10 AUI Input Pins RCV and CLSN pairs 11 AUI Output Pins TRMT pair 20 82503 DC CHARACTERISTICS Symbol (TC e 0 C to a 85 C VCC e 5V g5% VCCA e 5V g5%) (Continued) Min Max g150 Parameter Units mA mV mV mA mA mA mA W W mW pF Test Conditions Short Circuit to VCC or GND IOSC(AUI) AUI Output Short Circuit Current VU(AUI) ICC(HOT) ICC ICC ICCSB Output Differential Undershoot Power Supply Current(12) Power Supply Current Power Supply Current Standby Supply Current(13) VODI(AUI) Differential Idle Voltage(11) b 100 g40 65 75 60 1 0 38 0 40 5 25 10 APORT e 1 APORT e 1 APORT e 0 Low Power Mode 20 mA Typical APORT e 1 Continuous Transmission on AUI APORT e 1 Continuous Transmission on AUI Low Power Mode 105 mW Typical at f e 1 MHz PD (HOT) Power Dissipation(12) PD PDSB CIN(14) Power Dissipation Standby Power Dissipation(13) Input Capacitance NOTES 11 Measured 8 0 ms after last positive transition of data packet 12 ICC HOT measurements made at TC e a 85 C Additionally TRMT TRMT TDH TDH TDL TDL are loaded with 20 pF and load resistors removed 13 Pins CS0 and CS1 connected to VCC or VSS through a 2 5 kX (or less) resistor ICCSB is typically at 20 mA after 30s from power down assertion not tested 14 Characterized not tested (Controller interface and mode pins only ) AC TIMING CHARACTERISTICS 290421 - 9 290421 - 8 Figure 9 MOS Input Voltage Levels (TTL Compatible) for Timing Measurements (TxD RTS TPE AUI APORT APOL XSQ LID LPBK JABD TEST and RESET) Figure 10 Voltage Levels for MOS Level Output Timing Measurements (TxC RxD RxC CRS and CDT) 290421 - 10 290421 - 11 Figure 11 Voltage Levels for Differential Input Timing Measurements (RCV and CLSN Pairs) Figure 12 Voltage Levels for TRMT Pair Output Timing Measurements 21 82503 AC TIMING CHARACTERISTICS (Continued) 290421 - 13 290421 - 12 Figure 14 Voltage Levels for Differential Input Timing Measurements (RD Pair) Figure 13 Voltage Levels for TDH TDL TDH and TDL AC MEASUREMENT CONDITIONS 1 TC e 0 C to a 85 C VCC e 5V g5% 2 The AC MOS TTL and differential signals are referred to in Figures 8 9 10 11 12 and 13 3 AC loads a MOS 20 pF total capacitance to ground b AUI Differential a 10 pF total capacitance from each terminal to ground and a load resistor of 78X g1% in parallel with a 27 mH g1% inductor between terminals c TPE 20 pF total capacitance to ground 4 All parameters become valid 200 ms after the supply voltage and input clock has stabilized or after RESET deasserts CLOCK TIMING (15) Symbol t1 t2 t3 t4 t5 Parameter X1 Cycle Time X1 Fall Time X1 Rise Time X1 Low Time X1 High Time 15 15 Min 49 995 Typ Max 50 005 5 5 Units ns ns ns ns ns NOTE 15 Refers to External Clock Input 290421 - 14 Figure 15 X1 Input Voltage Levels for Timing Measurements 22 82503 Controller Interface Timings (Intel Mode) TRANSMIT TIMINGS (Intel) Symbol t10 t11 t12 t13 t14 t15 t16 t17 Parameter TxC Cycle Time TxC High Low Time TxC Rise Fall Time TxD and RTS Rise Fall Time TxD Setup Time to TxCv TxD Hold Time from TxCv RTS Setup Time to TxCv RTS Hold Time from TxCv 45 0 45 0 Min 99 99 40 5 10 Typ Max 100 01 Units ns ns ns ns ns ns ns ns 290421 - 15 Figure 16 Transmit Timing (Intel) 23 82503 RECEIVE TIMING (Intel) Symbol t20 t21 t22 t23 t24 t25 t26 t27 t28 RxC Cycle Time RxC High Time RxC Low Time RxC Rise Fall Time RxC Delay from CRSv RxD Rise Fall Time RxD Setup from RxCv RxD Hold from RxCv CRS Deassertion Hold Time from RxC High 30 30 10 40 1100 Parameter Min 96 36 40 5 1400 5 Typ 100 Max Units ns ns ns ns ns ns ns ns ns 290421 - 16 Figure 17 Receive Timing (Intel) 24 82503 Controller Interface Timings (National Mode) TRANSMIT TIMINGS (National) Symbol t30 t31 t32 t33 t34 t35 t36 Parameter TXC Cycle Time(16) TXC High Low Time TXC Rise Fall Time at 20% to 80% TXD Setup Time to TXCu TXD Hold Time from TXCu TXE Setup Time to TXCu TXE Hold Time from TXCu 20 0 20 0 Min 99 99 40 50 5 Typ Max 100 01 Units ns ns ns ns ns ns ns NOTE 16 All delay and width measurements on TxC are made at 1 5V 290421 - 17 Figure 18 Transmit Timing (National) 25 82503 RECEIVE TIMINGS (National) Symbol t40 t41 t42 t43 t44 t45 t46 t47 Parameter RxC Cycle Time RxC High Low Time(17) RxC Rise Fall Time at 20% to 80% RXD Rise Fall Time at 20% to 80% RXD Setup Time to RxCu RXD Hold Time from RxCu RxC Delay from CRSu RxC Continuing Beyond CRSv 30 20 1400 5 Min 96 40 Typ 100 50 60 5 5 Max Units ns ns ns ns ns ns ns cycles NOTE 17 All delay and width measurements on RXC are made at 1 5V 290421 - 18 Figure 19 Receiving Timings (National) 26 82503 Controller Interface Timing (AMD Mode) TRANSMIT TIMINGS(18) (AMD) Symbol t50 t51 t52 t53 t54 t55 t56 t57 Parameter TCLK Cycle Time TCLK High Time ( TCLK Low Time ( 0 8V to 2 0V) 2 0V to 0 8V) 0 8V to 2 0V) 20 5 20 5 Min 99 99 45 45 50 50 25 Typ Max 100 01 58 58 5 Units ns ns ns ns ns ns ns ns TCLK Rise Fall Time ( TX Setup Time to TCLKu TX Hold Time from TCLKu TENA Setup Time to TCLKu TENA Hold Time from TCLKu NOTE 18 Delay times for TX TENA and TCLK are measured from 0 8V for falling edges and 2 0V for rising edges 290421 - 19 Figure 20 Transmit Timings (AMD) 27 82503 RECEIVE TIMINGS(19) (AMD) Symbol t60 t61 t62 t63 t64 t65 t66 t67 t68 Parameter RCLK Cycle Time RCLK High Time ( RCLK Low Time ( 0 8V to 2 0V) 2 0V to 0 8V) 0 8V to 2 0V) Min 96 38 38 Typ 100 50 50 25 25 10 45 40 50 80 450 5 5 Max Units ns ns ns ns ns ns ns ns ns RCLK Rise Fall Time ( RX Rise Fall Time ( 0 8V to 2 0V) RX Hold time from RCLKu RX Setup Time to RCLKu RENA Deassertion Hold Time from RCLKu RCLK Delay from RENAu NOTE 19 Delay times for RX RENA and RCLK are measured from 0 8V for falling edges and 2 0V for rising edges 290421 - 20 Figure 21 Receive Timings (AMD Start of Frame) 290421 - 21 Figure 22 Receive Timings (AMD End of Frame) 28 82503 Controller Interface Timings (Fujitsu Mode) TRANSMIT TIMINGS (Fujitsu) Symbol t70 t71 t72 t73 t74 t75 t76 Parameter TCKN Cycle Time TCKN High Low Time(20) TCKN Rise Fall Time at 20% to 80% TXD Setup Time to TCKNv(20) TXD Hold Time from TCKNv(20) TEN Setup Time to TCKNv(20) TEN Hold Time from TCKNv(20) 20 0 20 0 Min 99 99 40 50 5 Typ Max 100 01 Units ns ns ns ns ns ns ns NOTE 20 Timing measurements are referenced at 1 5V level 290421 - 22 Figure 23 Transmit Timings (Fujitsu) 29 82503 RECEIVE TIMINGS (Fujitsu) Symbol t80 t81 t82 t83 t84 t85 t86 t87 t88 Parameter RCKN Cycle Time RCKN High Low Time(21) RCKN Rise Fall Time at 20% to 80% RXD Setup Time from RCKNv(21) RXD Hold Time from RCKNv(21) XCD Assertion Hold Time from RCKNv(21) XCD Deassertion Hold Time from RCKNv(21) XCD Deassertion Setup Time from RCKNv(21) RCKN Delay from XCDu(21) 20 10 0 10 120 80 130 1400 Min 96 35 Typ 100 50 60 5 Max Units ns ns ns ns ns ns ns ns ns NOTE 21 Timing measurements are referenced at 1 5V 290421 - 23 Figure 24 Receive Timings (Fujitsu Start of Frame) 290421 - 24 Figure 25 Receive Timings (Fujitsu End of Frame) 30 82503 TPE Timings TPE TRANSMIT TIMINGS Symbol t90 t91 t92 t93 t94 t95 t96 t97 t98 t99 t100 Parameter TxD to TD Bit Loss at Start of Packet TxD to TD Steady State Propagation Delay TxD to TD Startup Delay TDH and TDL Pairs Edge Skew ( VCC 2) 0 5V to VCC b 0 5V) 99 49 250 98 8 190 100 13 200 15 2 100 50 Min Typ Max 2 400 600 3 5 101 51 400 102 24 Units bits ns ns ns ns ns ns ns ns ms ns TDH and TDL Pairs Rise Fall Times ( TDH and TDL Pairs Bit Cell Center to Center TDH and TDL Pairs Bit Cell Center to Boundary TDH and TDL Pairs Return to Zero from Last TDHu Link Test Pulse Width Last TD Activity to Link Test Pulse Link Test Pulse to Data Separation 290421 - 25 Figure 26 TPE Transmit Timings (Start of Frame) 290421 - 26 Figure 27 TPE Transmit Timings (End of Frame) 31 82503 290421 - 27 Figure 28 TPE Transmit Timings (Link Test Pulse) TPE RECEIVE TIMINGS Symbol t105 t106 t107 t108 t109 t110 t111 t112 t113 Parameter RD to RxD Bit Loss at Start of Packet RD to RxD Invalid Bits Allowed at Start of Packet RD to RxD Steady State Propagation Delay RD to RxD Start UP Delay RD Pair Bit Cell Center Jitter RD Pair Bit Cell Boundary Jitter RD Pair Held High from Last Valid Positive Transition CRS Assertion Delay (Intel NS and Fuji Mode) (AMD Mode) CRS Deassertion Delay 230 Min 4 Typ Max 19 1 400 24 g13 5 g13 5 Units bits bits ns ms ns ns ns ns ns ns 400 700 1500 450 290421 - 28 Figure 29 TPE Receive Timings (Start of Frame) 32 82503 290421 - 29 Figure 30 TPE Receive Timings (End of Frame) TPE COLLISION TIMINGS Symbol t115 t116 t117 t118 Parameter Onset of Collision (RD Pair and RTS Active) to CDT Assert End of Collision (RD Pair or RTS Inactive) to CDT Deassert CDT Assert to RxD Sourced from RD Pair CDT Deassert (RD Pair Inactive) to RxD Sourced from TxD Min Typ Max 900 900 900 900 Units ns ns ns ns 290421 - 30 Figure 31 TPE Collision Timings (Start of Collision) 33 82503 290421 - 31 Figure 32 TPE Collision Timings (End of Collision) TPE LINK INTEGRITY TIMINGS Symbol t120 t121 t122 Parameter Last RD Activity to Link Fault (Link Loss Timer) Minimum Received Linkbeat Separation(20) Maximum Received Linkbeat Separation(21) Min 50 2 25 Typ 100 5 50 Max 150 7 150 Units ms ms ms NOTES 20 Linkbeats closer in time to this value are considered noise and are rejected 21 Linkbeats further apart in time than this value are not considered consecutive and are rejected 290421 - 32 Figure 33 TPE Link Integrity Timings 34 82503 AUI Timings AUI TRANSMIT TIMINGS Symbol t125 t126 t127 t128 t129 t130 Parameter TxD to TRMT Pair Steady State Propagation Delay TRMT Pair Rise Fall Times Bit Cell Center to Bit Cell Center of TRMT Pair Bit Cell Center to Bit Cell Boundary of TRMT Pair TRMT Pair Held at Positive Differential at Start of Idle TRMT Pair Return to s 40 mV from Last Positive Transition 99 5 49 5 200 80 3 100 50 Min Typ Max 200 5 100 5 50 5 Units ns ns ns ns ns ms 290421 - 33 Figure 34 AUI Transmit Timings AUI RECEIVE TIMINGS Symbol t135 t136 t137 t138 t139 t140 t141 t142 Parameter RCV Pair Rise Fall Times RCV Pair Bit Cell Center Jitter in Preamble RCV Pair Bit Cell Center Boundary Jitter in Data RCV Pair Idle Time after Transmission RCV Pair Return to Zero from Last Positive Transition CRS Assertion Delay (Intel National Fujitsu Modes) (AMD Mode) CRS Deassertion Delay CRS Inhibited after Frame Transmission 4 43 8 160 100 1050 350 5 Min Typ Max 10 g12 g18 Units ns ns ns ms ns ns ns ns ms 290421 - 34 Figure 35 AUI Receive Timings 35 82503 AUI COLLISION TIMINGS Symbol t145 t146 t147 t148 t149 t150 t151 Parameter CLSN Pair Cycle Time CLSN Pair Rise Fall Times CLSN Pair Return to Zero from Last Positive Transition CLSN Pair High Low Times CDT Assertion Time CDT Deassertion Time CRS Deassertion Time (Intel Mode Only RCV Pair Idle) 160 35 70 75 300 450 Min 80 Typ Max 118 10 Units ns ns ns ns ns ns ns 290421 - 35 Figure 36 AUI Collision Timings AUI NOISE FILTER TIMINGS Symbol t152 t153 Parameter RCV Pair Noise Filter Pulse Width Accept ( CLSN Pair Noise Filter Pulse Width Accept ( b 285 mV) b 285 mV) Min 25 25 Typ Max Units ns ns 290421 - 36 Figure 37 AUI Noise Filter Timings 36 82503 LOOPBACK TIMINGS Symbol t155 t156 t157 t158 t159 t160 Parameter TxD to RxD Bit Loss at Start of Packet TxD to RxD Steady State Propagation Delay TxD to RxD Startup Delay SQE Test Wait Time SQE Test Duration LPBK Setup Hold Times to RTS(22) 06 05 10 12 08 Min Typ Max 16 600 22 16 15 Units bits ns ms ms ms ms NOTE 22 Guarantees proper processing of transmitted packets Violation of this specification will not result in spurious data transmission Incoming data packets occuring during transitions on LPBK will not be accepted 290421 - 37 Figure 38 Loopback Timings 37 82503 JABBER TIMINGS Symbol t165 t166 t167 Parameter Maximum Length Transmission before Jabber Fault (TPE) Maximum Length Transmission before Jabber Fault (AUI) Minimum Idle Time to Clear Jabber Function Min 20 10 250 Typ 25 13 420 Max 150 18 750 Units ms ms ms 290421 - 38 Figure 39 Jabber Timings LED TIMINGS Symbol t170 t171 t172 t173 Parameter TxLED RxLED COLED On Time TxLED RxLED COLED Off Time LILED On Time LILED Off Time Min 50 50 50 100 Typ Max 450 Units ms ms ms ms 290421 - 39 Figure 40 LED Timings 38 82503 MODE TIMINGS(23 24) Symbol t175 t176 t177 t178 Parameter Mode Pins Setup to RTSv Mode Pins Hold from RTSu Mode Pins Setup to RD Active(25) Mode Pins Hold from RD Active(25) Min 100 100 100 100 Typ Max Units ms ms ms ms NOTES 23 Guarantees Proper processing of data packets Violation of these specifications will not affect the integrity of the network 24 Mode pins are APORT APOL XSQ LID JABD and TPE AUI 25 Any data received within 100 ms of a mode transmission will be considered invalid 290421 - 53 Figure 41 Mode Timings 39 82503 RESET TEST AND LOW POWER MODE TIMINGS Symbol t180 t181 t182 Parameter TEST and JABD Setup Time to RESETv RESET Pulse Width Low Power Mode Deactivation from TEST and JABDv Min 50 300 1 Typ Max Units ns ns ms 290421 - 41 Figure 42 Reset Timings (Test Mode) 290421 - 43 Figure 43 Reset Timings (Start of Low Power Mode) 290421 - 42 Figure 44 Reset Timings (End of Low Power Mode) 40 82503 PACKAGE DIMENSIONS PLASTIC LEADED CHIP CARRIER 290421 - 45 Figure 45 Principle Dimensions and Data 290421 - 46 Figure 46 Molded Details 41 82503 290421 - 47 Figure 47 Terminal Details 290421 - 48 Figure 48 Standard Package Bottom View (Tooling Option 1) 42 82503 290421 - 49 Figure 49 Standard Package Bottom View (Tooling Option II) 290421 - 50 Figure 50 Detail J Terminal Detail 43 82503 290421 - 51 Figure 51 Detail L Terminal Details NOTES The above diagrams use a 20-lead PLCC package to show symbols for package dimensions The table below indicates dimensions in mm that are specific to the 44-lead PLCC package 1 All dimensions and tolerances conform to ANSI Y14 5M-1982 2 Datum plane H located at top of mold parting line and coincident with top of lead where lead exits plastic body 3 Datums D - E and F- G to be determined where center leads exit plastic body at datum plane H 4 To be determined at seating plane C 5 Dimensions D1 and E1 do not include mold protrusion 6 Pin 1 identifier is located within one of the two defined zones 7 Locations to datum A and B to be determined at plane H 8 These two dimensions determine maximum angle of the lead for certain socket applications If unit is intended to be socketed it is advisable to review these dimensions with the socket supplier 9 Controlling dimension inch 10 All dimensions and tolerances include lead trim offset and lead plating finish 11 Tweezing surface planarity is defined as the furthest any lead on a side may be from the datum The datum is established by touching the outermost lead on that side and parallel to D -E or F -G Symbol A A1 D D1 D2 E E1 E2 CP TCP LT Overall Height Description Min 4 19 2 29 17 4 16 5 15 0 17 4 16 5 15 0 0 00 0 00 0 23 Max 4 57 3 05 17 7 16 7 16 0 17 7 16 7 16 0 0 10 0 10 0 38 Distance from Lead Shoulder to Seating Plane Overall Package Dimension Plastic Body Dimension Foot Print Overall Package Dimension Plastic Body Dimension Foot Print Seating Plans Coplanarity Tweezing Coplanarity Lead Thickness 44 82503 44-LEAD QUAD FLATPACK PACKAGE 290421 - 52 Figure 52 44-Lead Quad Flatpack Package Symbol A A1 B C D1 E1 e1 D E L1 Y T Description Package Height Stand Off Lead Width Lead Thickness Package Body Package Body Lead Pitch Terminal Dimension Terminal Dimension Foot Length Coplanarity Lead Angle 0 0 65 12 0 12 0 38 0 02 01 03 0 15 10 10 08 12 4 12 4 0 58 0 95 12 8 12 8 0 78 01 10 Min Nom Max 2 35 0 60 04 02 NOTE Unless otherwise specified all units are in millimeters 45 |
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